module top(input inc, dec, clk, rst, 
  output [6:0] led_d0,led_d1,led_m0,led_m1,led_y0,led_y1,led_y2,led_y3);

reg [7:0] day, month;
reg [11:0] year;

reg carry_month, carry_day;
reg [7:0] max_day;


reg [3:0] bcd_d0, bcd_d1, bcd_m0, bcd_m1, bcd_y0, bcd_y1, bcd_y2, bcd_y3;

  bcd8 bcd_day(day,bcd_d0,bcd_d1);
  bcd8 bcd_month(month,bcd_m0,bcd_m1);
  bcd12 bcd_year(year,bcd_y0,bcd_y1,bcd_y2,bcd_y3);

  a7_decoder digit_day0(bcd_d0,led_d0);
  a7_decoder digit_day1(bcd_d1,led_d1);
  a7_decoder digit_month0(bcd_d0,led_m0);
  a7_decoder digit_month1(bcd_d1,led_m1);
  a7_decoder digit_year0(bcd_d0,led_y0);
  a7_decoder digit_year1(bcd_d1,led_y1);
  a7_decoder digit_year2(bcd_d2,led_y2);
  a7_decoder digit_year3(bcd_d3,led_y3);

always @(posedge clk or posedge rst) begin

  if (rst) begin
    year <= 11'd2013;
    month <= 6'd1;
    day <= 6'd1;
  end
  else begin
    if (inc && !dec) begin
      get_max_day(month, max_day);
      inc_day(day, max_day, day, carry_day);
      inc_month(carry_day, month, month, carry_month);
      inc_year(carry_month, year, year);
    end
    else if (!inc && dec) begin
      get_last_max_day(month, max_day);
      dec_day(day, max_day, day, carry_day);
      dec_month(carry_day, month, month, carry_month);
      dec_year(carry_month, year, year);
    end
  end
end

endmodule
